Method and architecture for controlling asymmetry of an LMS adaptation algorithm that controls FIR filter coefficients

ABSTRACT

A circuit ( 48 ) and method, which can be used in a mass data storage device, controls adaptation asymmetry of coefficients of an FIR filter ( 20 ) using an accumulator ( 52 ) or accumulating correlation results between unequalized FIR filter input data samples and FIR filter output equalized error samples. A circuit ( 52 ) generates coefficient increment and decrement requests from the accumulated correlation results. A circuit ( 120,102′,122 ) updates the coefficients within a symmetric coefficient pair on the basis of the increment and decrement requests only if a predetermined nonzero coefficient magnitude difference between the coefficient pair would not be exceeded by the update. In one embodiment of the invention, circuit ( 52 ) and method are provided for generating coefficients for an FIR filter in a sign-sign LMS algorithm using an accumulator for accumulating in a sub-least significant bit register ( 54 ) successive sign values of an error between input data samples to the FIR filter and output error samples from the FIR filter and an increment/decrement circuit ( 64 ) to request an increment/decrement of a coefficient value of the FIR flter on the basis of carry-out and borrow-in operations of the sub-least significant bit register ( 54 ).

CROSS REFERENCES TO RELATED APPLICATIONS

[0001] This application claims the benefit of prior filed copendingprovisional application serial No. 60/122,219, filed Mar. 1, 1999.

[0002] This application is a continuation-in-part of copending patentapplication Ser. No. 09/224,364, filed Dec. 31, 1998, which is herebyincorporated by reference.

[0003] This application is a continuation-in-part of copending patentapplication Ser. No. 09/256,568, filed Feb. 24, 1999, which is herebyincorporated by reference.

[0004] This application is a continuation-in-part of copending parentapplication Ser. No. 09/258,045, filed Feb. 25, 1999, which is herebyincorporated by reference.

[0005] This application is a continuation-in-part of copending patentapplication Ser. No. 09/256,420, filed Feb. 24, 1999, wnich is herebyincorporated by reference.

[0006] This application is a continuation-in-part of copending patentapplication Ser. No. 09/258,594, filed Feb. 26, 1999, which is herebyincorporated by reference.

[0007] This application is a continuation-in-part of copending patentapplication Ser. No. 09/258,3927, filed Feb. 25, 1999, which is herebyincorporated by reference.

BACKGROUND OF THE INVENTION

[0008] 1. Field of the Invention

[0009] This invention relates to improvements in methods for operating amass data storage device having an FIR filter in a read channel thereofthat uses PRML equalization and dynamic coefficients, and moreparticularly to improvements in methods for modifying the dynamiccoefficients thereof, and to improvements in mass data storage devices,filters used therein in PRML equalization environments, and moreparticularly to circuits for modifying the dynamic coefficients thereof.

[0010] 2. Relevant Background

[0011] The PRML equalizaton of a magnetic recording read channel, isusually accomplished by a continuous-time filter, CTF, that isimplemented using analog technique, followed by a finite-impulseresponse filter, FIR. The FIR filter can be implemented in one of twoways: either in a sampoed analog fashion or in a pure digital fashion.In the former case, a sample-and-hold circuit separates the CTF and FIR,whereas in the latter case, an analog-to-digital converter, ADC,separates the two blocks.

[0012] The chief purpose of the CTF filter is to provide ananti-aliasing filter to limit the spectral contents of the signal andnoise beyond the Nyquist frequency. However, CTF filter are inherentlydifficult to tune and adapt. It is the FIR filter, nowadays that playsthe najor role in achieving a fine signal equalization to the desiredPRML targer. With the advent of deep sumicron CMMOS processes, thedigital FIR filters with sophisticated Least Mean Square, LMS,coefficient adaptation algorithms are becoming less and lest costly,whereas the analog CTF circuits do not scale down very well. The LMSadaptation fo FIR coefficients is customarilyu done using a sign-signLMS algorithm. Here, only a sign bit of the unequalized input datasample and a sign bit of the corresponding equalized output data sampleerror are used, instead of their full value representations.

[0013] Magneto-resistive heads have been recently more popular thantheir thin-film inductive head counterparts. This is due mainly to theirlower cost. However, their response transfer function is nonsymmetric orpositive and negative pulses, as well as the leading and trailing edges,and it exhibits a larger amount of nonlinearities.

[0014] There are two kinds of FIR cnnfigurations that are used to ensureits generally linear phase characteristic: odd- and even-symmetricity ofthe unit pulse response sequence. The linear phase property is requiredto minimize the frequency dispersion effects by nonlinear phase responsein any data transmission application. However, a slight deviation fromthe perfect coefficient symmetricity is beneficial to compensate for thenon-linear characteristics of MR heads and CTF filters.

[0015] Due to the problems of loop contention between the timingrecovery and FIR coefficients adaptatior loops, a symmetric-manner ofcoefficients adaqtation is usually enforced. Not doing so is likely tocause a “runaway” situation for both loops. Oven thougn the initial FIRcoefficient settings do not have to be symmetritc, the LMS adaptationwill be incomplete and not able to automatically compensate for thesignal nonlinearities.

SUMMARY OF THE INVENTION

[0016] The invention bridges the gap between the unrestrictedcoefficient adaptation that is capable of ccmpensating high amount ofsignal nonlinearities but is ikely to cause system instabilities, andthe symmetric coefficient adaptation constraint that ensures FIR groupdelay stability.

[0017] Thus, in accordance with a broad aspect of the invention, amethod for controllin adaptation asymetry of coefficients of an FIRfilter is presented in which the FIR coefficients are grouped intosymmetric pairs. Correlation results between unequalized FIR filterinput data samples and FIR filter equalized output error samples areaccumulated. Coefficient update information is generated from theaccumulated correlation results, and the coefficients within eachsymmetric pair are updated on the basis of the generated coefficientupdate information only if a nonzero limit of permitted coefficientasymmetry would not be exceeded by the update. The correlation resultsmay be accumulated as successive sign values of an error between inputsamples to and output error samples from the FIR filter, and thecoefficient update information may be generated by requesting anincrement and decrement of a coefficient value of the FIR filter on thebasis of carry-out and borrow-in operations of the least significant bitregister, respectively.

[0018] According to another broad aspect of the invention, a method ispresented for controlling adaptation asyimetry of coefficients of an FIRfilter following a continuous time filter for limiting signal aliasingbeyond the Nyquist frequency. The method includes grouping the FIRcoefficients into symmetric pairs to follow a unit pulse responseproperty of a linear phase response filter, and accumulating correlationresults between unequalized input data samples and equalized outputdecision error samples in a correlator filter. The method also includesgenerating FIR filter coefficient update requests from information fromthe correlator filter, and updating the coefficients within eachsymmetric pair on the basis of the generated update requests only if anonzeero limit of permitted coefficient asymmetry in the FIR would notbe exceeded. Accorcing to yet another broad aspect of the invention, amethod is presented for generating coefficients for an FIR filter in asign-sign LMS algorithm. The method includes accumulating in a sub-leastsignifIcant bit register successive sign values of an error betweeninput data samples to the FIR filter and output error samcles from theFIR filter. The method also includes, on the basis of carry-out andborrow-in operations of the least significant bit register, respectivelyrequesting an increment and decrement of a coefficient value of the FIRfilter.

[0019] According to still another broad aspect of the invention, acircuit is presented for controlling adaptation asymmetry ofcoefficients of an FIR filter. The circuit includes an accumulator foraccumulating correlation results between unequalized FIR filter inputdata samples and FIR filter output equalized error samples and a circuitfor generating coefficient increment and decrement requests from theaccumulated correlation results. A circuit updates he coefficientswithin a symmetric coefficient pair on the basis of the increment anddecrement requests only if a predetermined nonzero coefficient magnitudedifference between the coefficient pair would not be exceeded by theupdate. The circuit for updating the coefficients may include a circuitfor determining a coefficient magnitude difference between a coefficientpair, a decoder to determine if the coefficient magnitude difference hasnot exceeded a predetermined value, and an arbiter circuit for issuing acoefficient update instruction if the decoder has determined that thecoefficient magnitude difference has not exceeded the predeterminedvalue.

[0020] According to still yet another broad aspect of to invention, acircuit is presented for generating coefficlents for an FIR filter in asign-sign LMS algorithm that includes an accumulator for accumulating ina sub-least significant bit register successive sign values of an errorbetween input data samples to the FIR filter and output error samplesfrom the FIR filter an increment/decrement circuit requests anincrement/decrement of a coefficient value of the FIR filter on thebasis of carry-out and borrow-in operations of the least significant bitregister.

[0021] In accordance with yet another broad aspect of the invention, amass data storage device, having a read channel with an FIR filter, ispresented. The circuit has accumulator for accumulating correlationresults between unequalized FIR filter input data samples and FIR filteroutput equalized error samples. A circuit generates coefficientincrement and decrement requests from the accumulated correlationresults. A circuit updates the coefficients witnin a symmetriccoefficient pair on the basis of the increment and decrement recuestsonly if a predetermined nonzero coefficient magnitude difference betweenthe coefficient pair would not be exceeded by the update, wherein anadaptation asymmetry of coefficients of the FIR filter is controlled.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The invention is illustrated in the accompanying drawings, inwhich:

[0023]FIG. 1 is a block diagram of a circuit architecture for performinga sign-sign LMS FIR filter coefficient adaptation algorithm, inaccordance with a preferred embodiment of the invention.

[0024]FIG. 2 is a block diagram of a correlation filter of LMS sub-LSBcoefficients that may be used in the circuit of FIG. 1.

[0025]FIG. 3 is a state diagram of an LMS coefficient update statemachine, or requestor, that is employed in the operation of the circuitof FIG. 1.

[0026]FIG. 4 is a table showing the operation of successive incrementand decrement operations by the sub-LSB circuit for use in driving an MScoefficient update request, in accordance with a preferred embodiment ofthe invention.

[0027]FIG. 5 is a block diagram of an LMS coefficient pair differencestate machine that may be used in the circuit of FIG. 1.

[0028]FIG. 6 is a able showing the operation of the decoder of the statemachine of FIG. 5.

[0029]FIG. 7 is a schematic diagram of an update selection circuit thatmay be used in the implementation of the circuit of FIG. 6.

[0030]FIG. 8 is a schematic diagram or a multiplex circuit that may beused in the implementation of the circuit of FIG. 6.

[0031]FIG. 9 is a block diagram of a request and arbitration circuitthat may be used in the circuit of FIG. 1.

[0032] And FIG. 10 is a block diagram of an arbiter circuit that may beused in the circuit of FIG. 1.

[0033] In the various figures of the drawing, like reference numeralsare used to denote like or similar parts.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] The invention is based on the idea of controlled adaptationasymmetry of FIR coefficents. in this method, the FIR coefficients thatcomprise a symmetric pair are allowed to develop a certain controlledlimit of asymmetry. The limit on the amount of controlled asymmetryshould be set high enough to allow compensation of signal nonlinearitiesdue to the imperfections of, for example, MR heads and CTF filters, butat the same time be low enough not to cause any significant variationsin the FIR group delay.

[0035] According to a preferred embodiment of the invention, this isaccompished by grouping the FIR coefficients into symmetric pairs insuch a manner that it follows the unit pulse response property of linearphase response filters. Updates of both coefficients within eachsymmetricity par is controlled by an arbiter state machine that receivesupdate requests for both coefficients. The update requests are generatedseparately for each coefficient in a “tick” request handshaking statemachine that receives and processes coefficient upodate tick requestsfrom a correlator filter. The correlator filter accumulates thecorrelation results between the unequalized input data samples and theequalized output decision error samples.

[0036] More particularly, in the past, the filter coefficients of theFIR filter that is employed in the read channel of the mass data storagedevice are modified by a “sign-sign” least means squared (LMS)adaptation algorithm. It is known that the filte coefficients should besymmetrically modified in pairs in order to control the symmetry of theFIR filter. Thus, typically, the coefficients are grouped intooutside-to-inside pair groupings; for example, in an implementation inwhich eight FIR coefficients are employed, the coefficients aretypically grouped by associating coefficients numbered 0 and 7, 1 and 6,2 and 5, and 3 and 4. Then, when one of the coefficient is dynamicallymodified to change the filter characteristics of the FIR filter, bothcoefficients of the pair must be modified equally. The failure toequally, between the timing recovery loop and the FIR coefficientsadaptation loop. Moreover, by modifying the coefficients in pairs, thephase shift that might otherwise be intoduced by the FIR filter ismaintained to help ensure that the output from the FIR filter does notcompete with the timing recovery function.

[0037] A block diagram showing an overall “sign-sign” LMS adaptationalgorithm and architecture 10 according to a preferred embodiment of theinvention is sshown in FIG. 1. The architecture 10 receives a signalfrom, for example, a hard disk 12 of the type that may be found in massdata storage devices, for use with which the LMS adaptation algorithmand architecture is particularly well suited. Data from the hard disk 12is read, for instance, by a magneto-resistive head 14, or other suitabletransducer, and is filtered by a continuous time filter (CTF) 16. Thefiltered output from the CTF filter is then converted to a digitalsignal by an analog to digtal converter (ADC) 18 (a sample, hold, andquantize circuit). In the embodiment illustrated, the output from thedigitizer is provided in even and odd data streams to an FIR filter 20.The FIR filter 20 may, for example, be of even symmetric type havingeight filter coefficients to produce respective even and odd filteredoutputs. The even and odd filtered output are combined by areinterleaver circuit 22 to provide bit-rate equalied data samples onoutput line 24 for use in the read channel of the mass data storagedevice with which the circuit 10 is associated. The coefficients of theFIR filter 20 are dynamically adjusted in operation. More particularly,the sign bits of the unequalized data samples to the FIR filter 20 areprocessed, first by determining the sign bits of the odd and even inputsamples by sign determining circuit 26 and 28, respectively, then byreinterleaving the signals by a reinterleaver circuit 30. This providesa bit-rate stream of unequalized sign samples on line 32 at the outputof the reinterleaver 30. The signs are shifted through a serial shiftregister 34 to align them with the FIR-delayed equalized sample errors.

[0038] The serial shift register 3 , in the embodiment illustrated, has10 data sections, numbered 1-10. The outputs from data sections 3-10 areprovided to a correlator 40. The correlator 40 provides for each outputfrom the serial shift register sections 3-10 an exclusive-OR (XOR)functicn or comparison with the sign signal of the equalized samples onoutput line 24, which is developed by an error circuit 42 and signdetermining circuit 44. Thus, at each output station 3-10 of the serialshift registe 34, the correlator 40 provides an XOR comparison with thethen current sign of the equalized sample on output line 24. The XORoutputs are provided on lines 46 to a coefficient update ciruit 48,described below in detail. The coefficient update circuit 48 providesoutputs on lines 50 that represent updated FTR filter coefficients,which are fed back to the FIR filter 20.

[0039] More particularly, the outputs from the correlator 40 areprocessed in symmetric pairs to provide coeffcients to control the FIRfilter 20. For example, in the embodiment illustrated, the coefficientsare paired symmetrically, with coefficients [#2] and [#7], coefficients[#1] and [#6], coefficients [#2] and [#5], ana coefficients [#3] and[#4] being paired. As will become apparent, the respective coefficientpairs are constrained to be modifiable only in accordance with a valuethat will result in the pair being within a predetermined magnituderange difference of each other. For example, the coefficient pair[#0]-[#7] may be modified so that no more than a predetermined magnitudedifference, for example, of two, or other predetermined magnitudedifference, may result. If an update request is made that would resultin a larger magnitude difference than the predetermined value, it maynot be made. As a result, the symmetricity of the FIR filter 20 ismaintained within a predetermined value amount.

[0040] In contrast to the prior art, which accumulated entire LSBcorrelation results from the correlator, according to the invention, thecorrelation direcrion outputs 46 from the correlator 40 are accumulated,and, more particularly, are accumulated in sub-LSB accumularors 52, 52′.As used herein the term “LSB” refers to the Least significant bit (LSB)of the respective FIR coefficients themselves. In the sign-signadaptation algorithm, only an increment/decrement operation can beperformed on the parricular coefficient in question. Consequently,herein the term “sub-LSB” refers to a correlation filter accumulator hataccumulates only certain lower ordered portions of the correlationdirection outputs and which controls and directly affects the LSBs ofthe coefficients. Thus, as used herein, the sub-LSB and the correlationfiber accumulators are equivalent, and are referred to as “sub-CFaccumulators”. Therefore, as the correlation direction data streams nothe output lines 46 from the correlator 40 arrive at the sub-CFaccumulators, they are accumulated until either an overflow orunder-flow boundary is reached. Upon the occurrence of the overflow orunderflow condition, a request, herein referred to as a “tick”, is madeto increment or decrement the coefficient in the data stream in whichthe over-low or underflow occurred. As will become apparent the tick mayor may not be acted upon, depending upon tne existing difference thatwill result with the corresponding paired coefficient with which thecoefficient in the data stream in question is paired.

[0041] Details of the correlation filter and accumulator of the LMSsub-LSB coefficient accumulator 52 are shown in FIG. 2, to whichreference is now additionally made. Although only one accumulatorcircuit 52 is shown, it will be understood that similar circuits areemployed for each of the coefficient data paths. The accumulator 52includes a register 54, wnich is initially set to zero. The register 54contains the sub-least significant bits of the accumulated coefficient,which, in the embodiment shown, may be nine bits wide. The output fromthe register 54 is connected to the inputs of a multiplexer 56, afterhaving a step size value programmed or statically set and added orsubtracted therefrom by a step size precomputing section 60.

[0042] The upwardly or downwardly computed sub-LSB portion of thecoefficient is selected by the correlation direction signal on line 62from the correlator 40, shown in FIG. 1. The correlation direction iseither plus 1 or minus 1 to select either an increment or decrement tothe sub-LSB coefficIent. The overflow and underflow bits of the sub-LSBcoefficient are selected at the output of the multiplexer 36 on line 56,which indicates that an overflow or underflow conditions has occurred inthe operation of the accumulator circuit 32. The values of the overflowand underflow states are held in a register 64 and provided on outputlines 66 as a tick requester for either for an up increment or decrementof the overall FIR coefficient in the data stream containing theaccumulator 52.

[0043] Additionally, the output containing the sub-LSB coefficient fromthe multiplexer 56 is returned on lines 70 to the register 54 to updateits contents. In the embodiment illustrated, a second multiplexer 72 maybe provided to select between an operation including the sub-LSBcoefficient updates, described above, or an operation which does notinclude the sub-LSB updates, depending upon the state of the signal onselection line 74. Moreover, resetting the register 54 may be controlledby a signal from an arbitrator, below described in detail, and by theoverflow signal on line 58 via an AND gate 76.

[0044] A state diagram explaning the operation of the LMS coefficientupdate requester is shown in FIG. 3, to Which reference is nowadditionally made. The state diagram shows the output values Q1 ano Q0in each of three scares. A “1” or high state reoresents a recuest toincrement (Q1) or decrement (Q0) a coefficient, and a “0” or low staterepresents no action. The initial state 80 represents a state in whnchno request has been issued.

[0045] When a SUBOF_UP input (generated on line 66 of the correlationfilter 52 shown in FIG. 2) is received, the requestor changes to state82, in which Q1 is high, but Q0 is low. If a subsequent SUB_OF up signalor nothing is received, the requestor remains in state 82. From state32, if a down request, SUB_OF down, is received, the requestor movesback to state 80 until the next input is received. If the next input isan UP input, the state of the requestor returns to state 82. On theother hand, if a DN input is received, the state moves to down state 84,in which the state of Q1 is low and the state of Q0 is high. Asubsequent down input, or no input at all, does not change the state ofthe requestor, which remains in state 84. On the other hand, an up inputor clear input returns the requestor state to the Initial state 80 whereboth Q1 and Q0 are low.

[0046] Still more particularly, the operation of the accumulator 52 isillustrated in the chart of FIG. 4. The data illustrated in FIG. 4 isfor a four-bit accumulator; however, those skilled in the art willrecognize that other sized accumulators can equally advantageously beemployed. (It is noted, for example, that the size of the accumulatorillustrated in FIG. 2 is nine bits wide.) In the operation of theaccumulator, as each increment tick request is received, the accumulatormoves from an intial state 90 one state to the right in the direction ofa final overflow value state 92. When the state 92 is reached, theoverflow condition thereof is set, enabling the accumulator to issue atick request to increment the LMS coefficient.

[0047] On the other hand, when a decrement indication is received, theaccumulator moves with each indication one step to the left, until afinal underflow state 94 is reached. At that point, the accumulator ispermitted to issue a decrement tick request, and is reset back to theinitial state 90.

[0048] It should be noted that the increment and decrement indicationsare provided by the +1 −1 signals from the correlation directionproduced by the correlator 40, shown in FIG. 1. Thus, a vuffer-likeaction is provided by the manner of operationof the accumulator 52 byvirtue of the provision of a number of intermediate states that must betraversed before the final overflow or underflow state 92 or 94respectively may be reached. In fact, if only a few incrementindications are received followed by a few decrement indications and soon the overflow and underflow states may never be reached, and, theaccumulator may never issue an increment or decrement tick request.

[0049] IT should also be emphasized, as above mentioned, that the factthat the accumulator has issued an increment or decrement tick requestdoes not automatically guarantee the tick request will be fulfilled. Therequest, according to a preferred embodiment of the invention, may onlybe acted upon if it results in an increment or decrement of thecoefficient that is within the permitted range of its companion orpaired coefficients.

[0050] For example, if a predefined range difference of pairedcoefficients is two, and, for instance, coefficient [#0] is alreadyspaced a distance of 1 in magnitude from its paired coefficient [#7], arequest to increment coefficient [#0] by 1 may be permitted, since suchincrement would increase the spacing between coefficiet [#0] andcoefficient [#7] to a separation distance of 2.

[0051] However, if a subsequent increment request is received toincrement the magnitude of coefficient [#0], without a concomitantrequest to increase the magnitude of coefficient [#7], the incrementrequest cannot be performed. In such case, however, a decrement requestcan be performed on coefficient [#0], since that would bring thedifferenrce between coefficient [#0] and coefficient [#7] to a value ofonly 1. Additionally, if a range difference of 2 exists and a decrementrequest is issued to decrement coefficient [#7], that request wouldincrease the range to beyond the predetermined range value allowed,i.e., 2, and the request cannot be accomodated.

[0052] This arrangement, therefore, allows for some flexibility in themodification of the FIR coefficients, that allowed a modification of oneof the pair of coefficients only with a corresponding modificacion tothe other of the pair. Thu, the timing loop and the LMS. coefficientloops, by proper definition of the allowed range berween coefficientpair values, should be enabled to properly converge on the prorercoefficient values of the FIR filter.

[0053] The establishment of the range of permitted values isaccomplished in the embodiment illustrated by a state difference statemachine 90, illustrated in FIG. 5, to which, reference is nowadditionaly made. In the coefficient pair difference state machine 90, adecoder 94 is provided that maintains a look up table to pass on apermitted increment (GATE_UP) or decrement GATE_DN) request that enablesvia an arbiter circuit below described in detail with respect to FIGS.9-10) the increment/decrement circuit 124 (see FIG. 1) to operate.

[0054] The pair difference state machine 90 includes a resister 92 thatis initally reset. The output from the register 92 is connected to theinput of the decoder 94, as described above. The output from theregister 92 is additionally fed back to itself through a multiplexer 102through restective addition circuits 104. The selection of themultiplexer input is made by signals on a select line 106 which aregenerated according to the selection circuit 110 of FIG. 7, the inputsof which being derived by rising edge detectors (not shown) that detectthe U0_GATED, D0_GATED, U1_GATED and D1_GATED signal of FIG. 10.

[0055] Thus, for example, if a request is made that would result in anincrease of −2 to the value contained in the register 92, the selectioncircuit 110 shown in FIG. 8 provides select signals on line 106 toselect the +2 input of the multiplexer 102. (It is noted that theaddition circuits 104 precalculate the various allowedincrement/decrement differences before the selection process carried outby the multiplexer to increase the speed of the overall selectionprocess.) The output of the multiplexer 102 is then applied to theregister 92, which then holds the new value for the decoder 94. thecircuit 102 of FIG. 8 shows a circuit level diagram for theimplementation of the multiplexer 102 and its respective input value.

[0056] The operation of the 94 is illustrated with respect to the tableshown in FIG. 6, to which reference is now additionally made. Asmentioned, the decoder 94 may be a look up table that decodes the rangedifference established in the register 92 to provide gate up and gatedown signals on output lines 98 and 100 when the difference is less thanthe predetermined range difference. The table in FIG. 6 shows, forexample, three possible decoded range value, denoted “LO”, and “HI”,which represent allowed difference ranges of 2, 4, and 7, respectively,although, of course, any range value may be used. The range may beselected by applying a selected signal on line 96 to the decoder 94from, for example, a user programmable memory (not snown).

[0057] With reference, for example, to the mid range column, “MID” itcan be seen that if the output from the register 92 that is applied tothe decoder 94 is within a range of plus or minus 2, the up or downenabling valves are set. However, once the value contained in theregister 92 exceeds plus 2, only the signal on the gate down line may beenabled. This means that only a recuest for a down movement of thecoefficient in question may be affected. On the other hand, if the valuecontained in the register 92 is less than −2, only an up value can beeffected.

[0058] The “LO” and “HI” ranges, if implemented, operate in the samemanner as the “MID” range described, but the ranges are less andgreater, respectively, than the “MID” range.

[0059] The construction of the accumulation, arbitration, andincrement/decrement portion 48 of the circuit shown in FIG. 1 is shownin greater detail in FIG. 3, to which reference is now additionallymade. illustrated is a circuit that is associated with a single pair ofcoefficients, for example, coefficients [#0] and [#7]. Similar circuits,not shown, are provided for the remaining paired coefficients, in theembodiment Illustrated, including coefficients [#1] and [#6],coefficients [#2] and [#5], and coefficients [#3] and [#4].

[0060] The output signals on lines 62 and 62′ from the correlator 40(FIG. 1) are shown as inputs to the SUBOF accumulator circuits 52 and52′, which produce one SUBOF increment or decrement tick requests to therequestor circuits 120 and 120′. The requestor circuits :20 and 120′provide the increment and decrement tick requests to an arbiter cIrcui122, whIch outputs arbitration update strobe and direction instructionsto increment or decrement the coefficients in boxes 124 and 124′

[0061] Details of the arbiter circuit 122 are shown in greater detail inFIG. 10, to which reference is now additionally made. Inputs to thearbiter circuit 122 are provided on lines 121, which are morespecifically numbered 126-127 and 129-130 representing the up and downsignals provided from the requesters 120 and 120′. The signals on therespective up lines 126 and 129 are compared by AND gate 132, the outputof which represents a request for an increment of both coefficients [#0]and [#7], which would not affect the range value therebetween, andwhich, therefore, would be automatically allowed.

[0062] In a similar fashion, the signals on lines 127 and 13C arecompared by an AND gate 134, the output of which represents anindication that both coefficient [#0] and [#7] are requested to bedecremented, which also is automatically allowed.

[0063] The uptate strobe and direction of the operation to be preformedis determined by the circuit 140, which, in each channel, provides apair of multiplexers 141 and 142 and an AND gate 143. Each AND gatereceives the gate up/down enable signals from the LMS coefficient pairdifference state machine 90 above described, together with the tickrequest signal on one of lines 126-127 and 129-130. Thus, if the gateup/down enable signal is set, and a signal appears on a respective oneof lines 126-127 and 129-130, the request is passed to the and gate 143and the multiplexer 142 in its respective path. Each of the AND gates143 also receive the GATE_UP or GATE_DN signal from the decoder 94 ofFIG. 5, as shown. The outputs from the AND gates 143 are connected tothe default input of the multiplexers 141.

[0064] The signal selection of the pass states of multiplexers 141 and142 is controlled by the signals labeled MEM_LMS_SYM and MEM_LMS_DIF.The MEM_LMS_SYM controls whether or not the circuit 122 maintains thesymmetry of the FIR coefficients. Thus, if MEM_LMS_SYM is “1”, theoutput from the multiplexers 141 are selected. Otherwise, if MENMLMS_SYMis “0”, a brute force operation is selected, in which the signals onlines 126-127 and 129-130 pass, regardless of the affect that they willhave on the FIR coefficient symmetry.

[0065] Additionally, the signal MEM_LMS_DIF is applied to control thepass state of the multiplexers 141. (MEM_LMS_DIF is the stateprogrammable range selection signal described above with reference toFIGS. 5 and 6.) If both states are low, and symmetry is selected by ahigh state of MEM_LMS_SYM, only a request to increment or decrement bothof the coefficient pair occurs. Otherwise, the default state of themultiplexers 141 is selected, which controls the limit of asymmetryallowed to occur in the coefficient pairs.

[0066] It should be noted that even when the mode of operation oLf thearbiter 122 is similar to the prior art in which only perfect symmetrybetween coefficient pairs is allowed (MEN_LMS_SYM is “1” and MEM_LMS_DIFis “00”), the circuit 10 provides the advantage that theincrement/decrement requests are not lost. For example if an up (ordown) request is made to one coefficient, and a down, no, or up requestis made to the other, in the past, no action would have been taken, andthe requests would have been lost. According to the invention, therequests are accumulated, as above described, so suchincrement/decrement scenario made to only one of the coefficients wouldbe held until the other coefficient “caught up”, or received acorresponding increment or decrement request that would result inpreserving perfect symmetry of the coefficients.

[0067] The signals that are provided from the gating sage 140 are thenseparated into update strobe and a direction signal by logic stage 144,which provides the update strobe and direction to each of the incrementand decrement circuits 124 and 124′, which modify the coefficients andapplies them back to the FIR filter 20 (FIG. 1)

[0068] Althouah the invention has been described and illustrated with acertain degree of particularity, it is understood that the presentdisclosure has been made only by way of example, and that numerouschanges in the combination and arrangement of parts can be resorted toby those skilled in the art without departing from the spirit and scopeof the invention, as hereinafter claimed.

1. A method for controlling adaptation asymmetry of coefficients of anFIR filter, comprising: grouping the FIR coefficients into symmetricpairs; accumulating correlation results between unequalized FIR filterinput data samples and FIR filter equalized output error samples;generating coefficient update information from the accumulatedcorrelation results; and updating the coefficients within each symmetricpair on the basis of said generated coefficient update information onlyif a current coefficient asymmetry is within a predetermined limit. 2.The method of claim 1 wherein said coefficient update information is arequest to increment or decrement a value of a coefficient of the FIR.3. The method or claim 1 wherein said grouping comprises grouping saidFIR coefficients to follow a unit pulse response property of a linearphase response filter.
 4. The method of claim 1 wherein saidaccumulating correlation results comprises filtering the correlationresults in a correlator filter.
 5. The method of claim 4 wherein saidlimit of said permitted coetficient is a difference limit betweenpredetermined pairs of FIR filter coefficients.
 6. The method of claim 1wherein said controlling adaptation asymmetry of coefficients of an FIRfilter performed in a read channel of a mass data storage device.
 7. Themethod of claim 1 wherein said accumulating correlation resultscomprises accumulating in a sub-least significant bit registersuccessive sign values of an correlation between input data samples tosaid FTR filter and output error samples from said FIR filter; andwherein said generating coefficient update information comprisesrequesting an increment and decrement of a coefficient value of said FIRfilter on the basis of carry-out and borrow-in operations of saidsub-least significant bit register, respectively.
 8. A method forcontrolling adaptation asymmetry of coefficients of an FIR filterfollowing a continuous time filter for limiting signal aliasing beyondthe Nyquist frequency, comprising: grouping the FIR coefficients intosymmetric pairs to follow a unit pulse response property of a linearphase response filter; accumulating correlation results betweenunequalized input data samples and equalized output decision errorsamples in a correlator filter; generating FIR filter coefficient updaterequests from information from the correlator filter; and updating thecoefficients within each symmetric pair on the basis of said generatedupdate requests only if a nonzero limit of permitted coefficientasymmetry in said FIR would not be exceeded.
 9. The method of claim 8wherein said updating is performed only if a current coefficientasymmetry is within a predetermined limit.
 10. The method of claim 8wherein said controlling adaptation asymmetry of coefficients of an FIRis performed in a read channel of a mass data storage device.
 11. Amethod for generating coefficients for an FIR Filter in a sign-sign LMSalgorithm, comprising: accumulating in a sub-least significant bitregister successive sign values of a correlation between input datasamples to said FIR filter and output error samples from said FIRfilter; and on the basis of carry-out and borrow-in operations of saidsub-least sfgnificant bit register, respectively requesting an incrementand decrement of a coefficient value of said FIR filter.
 12. The methodof claim 11 further comprising determining a difference between a pairof FIR filter coefficients, and permltting the increment and decrementonly if said difference is less than a nonzero predetermined amount. 13.The method of claim 11 wherein said generating coefficients for an FIRis performed in a read channel of a mass data storage device.
 14. Acircuit for controlling Adaptation asymmetry of coefficients of an FIRfilter, ccmprising: an accumulator for accumulating correlation resultsbetween unequalized FIR filter input data samples and FIR filter outputequalized error samples; a circuit for generating coefficient incrementand decrement requests from the accumulated correlation results; and acircuit for updating the coefficients within a symmetric coefficientpair on the basis of said increment and decrement requests only if acurrent coefficient asymmetry is within a predetermined limit.
 15. Thecircuit of claim 1 wherein said circuit for updating the coefficientscomprises: a circuit for determining a coefficient magnitude differencebetween a coefficient pair; a decoder to determine if said coefficientmagnitude difference has not exceeded a predetermined value; and anarbiter circuit for issuing a coefficient update instruction if saiddecoder has determined that said coefficient magnitude difference hasnot exceeded the Predetermined value.
 16. The circuit of claim 14wherein said circuit is in a read channel of a mass data storace device.17. A circuit for generating coefficients for an FIR filter in asign-sign LMS algorithm, comprising: an accumulator for accumulating ina least significant bit register successive sign values of an errorbetween input data samples to said FIR filter and output error samplesfrom said FIR filter; and an increment/decrement circuit to request anincrement/decrement of a coefficient value of said FIR filter on thebasis of carry-out and borrow-in operations of said least sgnificant bitregister.
 18. The circuit of claim 17 further comprising a circuit todetermine a difference between a pair of FIR filter coefficients, and acircuit to permit the increment/decrement only if said difference isless than a nonzero predetermined amount.
 19. The circuit of claim 17wrerein said circuit is in a read channel of a mass data storage device.20. A mass data storage device, having a read channel with an FIRfilter, comprising: an accumulator for accumulating correlation resultbetween unequalized FIR filter input data samples and FIR filter outputequalized error samples; a circuit for generating cefficient incrementand decrement requests from the accumulated correlation results; and acircuit for updating the coefficients within a symmetric coefficientpair on the basis of said increment and decrement requests only if apredetermined nonzero coefficient magnitude difference between saidcoefficient pair would not be exceeced by the update, wherein anadaptation asymmetry of coefficients of said FIR rilter is controlled.21. The mass data storage device of claim 20 wherein said circuit forupdating the coefficients comprises: a circuit for determining acoefficient magnitude difference between a coefficient pair; a decoderto determine if said coefficient magnitude difference has not exceeced apredetermined value; and an arbiter circuit for issuing a coefficientupdate instruction if said decoder has determined that said coefficientmagnitude difference has not exceeded the predetermined value.
 22. Themass data storage device of claim 20 wherein said circuit for updatingthe coefficients comprises: a circuit for derermining a coefficientmagnitude difference between a coefficient pair; a decoder to determineif said coefficient magnitude difference has not exceeced apredetermined value; and an arbiter circuit for issuing a coefficientupdate instruction if said decoder has determined that said coefficientmagnitude difference has not exceeded the predetermined value.